1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) and a method for manufacturing the same, and more particularly, to a liquid crystal display having a thin film transistor and a method for manufacturing the same.
2. Discussion of the Related Art
Recently, among various display devices for displaying picture information, a flat panel display device has been developed due to its advantages of light weight and portability. Among others, the development of an LCD is one of the most active research areas. This is because an LCD can provide a high quality image, a high resolution, and a high response speed necessary to display motion pictures.
The principle of an LCD resides in optical polarity and anisotropy of a liquid crystal. Transmission of a light is controlled by giving an optical anisotropy to liquid crystal molecules; aligning the liquid crystal molecules in different orientations using the polar nature of the liquid crystal molecules. An LCD is composed of two transparent substrates separated by a certain distance. A liquid crystal material is injected into the space between the substrates on which various elements are formed to drive the liquid crystal. In general, thin film elements such as thin film transistors are manufactured on one of the substrates (thin film transistor substrate). Therefore, the performance of an LCD depends significantly upon the method of manufacture and the structure of such thin film elements. Moreover, an active matrix liquid crystal display (AMLCD), which has recently been commercialized, shows various performance fluctuations depending on the method of manufacture and the structure of the thin film transistor and other related elements. The details of a conventional active matrix liquid crystal display will be described below.
First, referring to FIG. 1, the structure of a conventional AMLCD is reviewed. Rectangular pixels, each of which represents a point of picture information, are disposed to form a matrix array. Gate bus lines 15 and signal bus lines 25 are arranged in columns and rows defining the array. At the intersection between the gate bus line and the signal bus line, a switching element is formed. In general, a thin film transistor (TFT) is used as the switching element. The source electrode 23 of the TFT is connected to the signal bus line 25 (source bus line or data bus line) and the gate electrode 13 of the TFT is connected to the gate bus line 15. A pixel electrode 31 and a common electrode are formed at each pixel to apply an electric field to the liquid crystal. The pixel electrode 31 is connected to the drain electrode 27 of the TFT. Therefore, when the TFT is turned on by applying appropriate voltages to the gate and signal bus lines, the signal voltage is applied to the pixel electrode 31. This voltage creates an electric field between the pixel electrode and the common electrode. Then, the electric field forces the liquid crystal molecules to align in a certain orientation which depends on the field direction. Therefore, transmission of a light can be controlled by an artificial control of the orientation of the liquid crystal molecules. This characteristic of a liquid crystal is utilized to display picture information.
Second, a method for manufacturing a conventional AMLCD is reviewed. Two transparent substrates are prepared to construct an LCD. In general, the substrates are made of non-alkaline or soda glass. Different processes are applied to the two substrates. On the first substrate (upper plate), a color filter layer, a black matrix, common electrodes, and bus lines are formed. On the second substrate (lower plate), switching elements such as TFTs, pixel electrodes, and bus lines are formed.
This invention particularly relates to a second substrate of an AMLCD, on which TFTs are formed. Therefore, conventional methods for manufacturing the second substrate will be mainly described below.
There are various AMLCDs depending on the method of manufacture and the structure. The AMLCDs can be classified according to the structure of a TFT. Typical structures of TFTs for an LCD are illustrated in FIGS. 2A to 5G.
FIGS. 2A to 2F, taken along the line I--I in FIG. 1, show an inverse staggered TFT, which uses amorphous silicon (a-Si) as a semiconductor layer. The method of manufacturing the inverse staggered TFT is as follows. A first metal, such as Ti, Cr, Ta, Al, Ti-Mo, Mo-Ta, or Al-Ta, (1000 to 2000 .ANG. thick) is deposited on a glass substrate 11. The metal is patterned to form a gate bus line 15 and a gate electrode 13(FIG. 2A), followed by the overall deposition of silicon nitride (SiN.sub.x) to form a gate insulation layer 17 (FIG. 2B). A thin film of an amorphous semiconductor material such as a-Si and a thin film of an impurity-doped amorphous semiconductor material such as n.sup.+ a-Si are sequentially deposited (1500 to 2000 .ANG. thick and 300 to 500 .ANG. thick, respectively) on the gate insulation film 17. They are patterned to form a semiconductor layer 19 and an impurity-doped semiconductor layer 21, as shown in FIG. 2B. Then, a second metal such as Cr, Mo, Ti, or Cr-Al (1000 to 2000 .ANG. thick)is deposited and patterned to form a signal bus line 25, a source electrode 23, and a drain electrode 27. The exposed portion of the impurity-doped semiconductor layer 21 is removed using the source and drain electrodes as a mask. At this moment, the impurity-doped semiconductor layer 21 makes an ohmic contact with the source electrode 23 and the drain electrode 27 (FIG. 2C). Next, silicon nitride (SiN.sub.x) is deposited to form a protection film 29 protecting the TFT formed under the film and providing an electrical insulation of the TFT from liquid crystal. Then, a contact hole is formed in the protection film 29 over the drain electrode 27, for connecting the drain electrode 27 to a pixel electrode, as shown in FIG. 2D. Indium tin oxide (ITO) 500 to 1000 A thick, conducting metal, is deposited and patterned to form a pixel electrode 31, as shown in FIG. 2E. This completes the manufacture of the inverse staggered TFT.
Here, when removing the impurity-doped semiconducting layer 21 located between a source electrode and a drain electrode, a silicon nitride layer may be formed as an etch stopper 35 to prevent the over-etching of the semiconducting layer 19, as shown in FIG. 2F.
FIGS. 3A to 3D show a staggered TFT, which uses an amorphous silicon (a-Si) as the semiconductor layer. The structure is inverse to the inverse staggered TFT described above. The method of manufacturing a staggered TFT structure is as follows. A first metal and an impurity-doped semiconductor material are deposited on a glass substrate 11. They are patterned to form a signal bus line 25, a source electrode 23, a drain electrode 27, and an impurity-doped semiconductor layer 21, as shown in FIG. 3A. Then, an amorphous silicon material, an insulation material such as SiNx or Si0.sub.2, and a second metal are sequentially deposited on the whole substrate including the impurity-doped semiconductor layer, and patterned at once to form a semiconductor layer 19, a gate insulation layer 17, a gate bus line (not shown in the drawings) and a gate electrode 13, respectively. The exposed portion of the impurity-doped semiconductor layer 21 is then removed, as shown in FIG. 3B. Here, the impurity-doped semiconductor layer 21 makes an ohmic contact with the source electrode 23 and the drain electrode 27. Next, a protection layer 29 is formed on the overall surface (FIG. 3C). A contact hole is formed in the protection layer 29 above the drain electrode 27. Finally, a pixel electrode 31 is formed and connected to the drain electrode 27 through the contact hole (FIG. 3D). This completes the manufacture of the staggered TFT.
FIGS. 4A to 4D show a coplanar TFT which uses polycrystalline silicon intrinsic semiconductor material (Poly-Si) as the semiconductor layer. The method for manufacturing a coplanar is as follows. A polycrystalline semiconductor material such as poly-Si and an impurity-doped polycrystalline semiconductor material are sequentially deposited on a transparent glass substrate 11 and patterned to form a semiconductor layer 19 and an impurity-doped semiconductor layer 21, as shown in FIG. 4A. Then, a first metal such as Al or an Al alloy is deposited and patterned to form a signal bus line 25, a source electrode 23 and a drain electrode 27. Subsequently, the exposed portion of the impurity-doped semiconductor layer 21 located between the source and drain electrodes is removed (FIG. 4B). Here, the impurity-doped semiconductor layer 21 makes an ohmic contact with the source and drain electrodes. Next, silicon oxide (SiO.sub.2) is deposited and patterned to form a gate insulation layer 17. Subsequently, a second metal such as Cr is deposited and patterned to form a gate bus line and a gate electrode 13. Then, silicon oxide (SiO.sub.2) is deposited to form a protection film 29, as shown in FIG. 4C. A contact hole is formed in the protection film 29 on the drain electrode 27. Finally, a pixel electrode 31 is formed by the deposition and patterning of ITO and connected to the drain electrode 27 through the contact hole (FIG. 4D). This completes the manufacture of the coplanar TFT.
FIGS. 5A to 5G show a self-aligned TFT. The method for manufacturing a self-aligned TFT is as follows. A semiconductor layer 19 is formed on a transparent substrate 11 by depositing and patterning a polycrystalline intrinsic semiconductor material. There are three methods to form a polycrystalline semiconductor layer, in general. First, polycrystalline silicon is formed by depositing and patterning an amorphous silicon and annealing it by laser. Second, polycrystalline silicon is formed by depositing an amorphous silicon and thermally annealing it. Third, a polycrystalline silicon material is directly deposited. After forming the semiconductor layer 19, silicon oxide and a first metal are sequentially deposited and patterned to form a gate insulation layer 17, a gate electrode 13, and a gate bus line (not shown in the drawings) as shown in FIG. 5B. At this time, the gate electrode 13 and the gate insulation layer 17 should be formed substantially at the center of the semiconductor layer 19. As shown in FIG. 5C, the edge portion of the semiconductor layer 19 are turned into a first impurity-doped semiconductor layers 21 by injecting impurity-ions into the semiconductor layer 19 using the gate electrode 13 as a mask (impurity concentration of 10.sup.14 to 10.sup.16 cm.sup.-3). Then, a photoresist is coated to cover a desired portion of the first impurity-doped semiconductor layer 21. Subsequently, as shown in FIG. 5D, a second impurity-doped semiconductor layer 21' is formed by injecting impurity-ions (impurity concentration of 10.sup.16 to 10.sup.18 cm.sup.-3). The first impurity-doped semiconductor layer 21 is a lightly-doped drain (LDD) part with impurity ions having lower density than the second impurity-doped semiconductor layer 21'.
Here, the impurity injecting step described with reference to FIG. 5C can be omitted. In this case, a photoresist is coated to cover a certain part of the semiconductor layer 19, an impurity doped semiconductor layer 21' is formed by injecting impurityions (impurity concentration of 10.sup.16 to 10.sup.18 cm.sup.-3). The part covered by the photoresist becomes an offset part with no injected ions.
Next, a first protection film 29 is formed by depositing silicon oxide on the whole surface, as shown in FIG. 5E. First contact holes are formed in the protection film 29. A second metal is deposited and patterned to form a signal bus line 25, a source electrode 23, and a drain electrode 27, which are connected to the impurity-doped semiconductor layer 21' through the contact holes. Then, ITO is deposited and patterned to form a pixel electrode 31 connected to the drain electrode 27, as shown in FIG. 5F. Alternatively, a second protection film 33 covering the source and drain electrodes may be deposited on the whole surface after depositing and patterning the second metal, and then a second contact hole and the pixel electrode may be formed (FIG. 5G).
The above-described conventional AMLCDs have the following drawbacks. First, as shown in FIG. 6, a stepped surface appears due to a multilayer structure of the TFT and bus lines. The figure shows the structure in which the gate insulation layer 17 is deposited on the gate bus line 15, and the signal bus line 25 is formed so as to cross the gate bus line. Thus, line disconnection and short circuit may occur at the intersection between the signal bus line and the gate bus line. Second, high parasitic capacitance is generated when a pixel electrode overlaps one of the bus lines, because an inorganic film such as SiN.sub.x or SiO.sub.x has a relatively high dielectric constant. Therefore, a pixel electrode is formed so as to have a predetermined space between the pixel electrode and the bus lines, as shown in FIG. 1. In this case, since the backscattered light passing through the space is undesirable, a black matrix, which blocks the backscattered light, is formed to cover the space between the bus line and the pixel electrode. This structure, however, has an insufficient aperture ratio. Third, after coating an alignment film for liquid crystal, a rubbing process is necessary for setting a pre-tilting angle in the alignment film, which determines the initial orientation of liquid crystal. The rubbing process, however, does not work properly on a surface with significant steps, and a domain phenomenon occurs and yields a different orientation from the intended one, which reduces the quality of the LCD.
The best or at least a good solution to these problems is to smooth the stepped profile due to the multilayer structure. Using a material having a high planarization property for a gate insulation layer and/or a protection film achieves this purpose.
Examples of such material having the high planarization property have been introduced in Japanese patents: 4-163528, 83-289965, 4-68318, and 63-279228.
These patents use polyimide or acryl resin as a protection film in order to obtain a smooth surface over the TFT. However, since the adhesion property between the resins and ITO (a pixel electrode) is poor, it is necessary to form a thin intermediate layer of an inorganic material prior to the ITO deposition to prevent the detachment of ITO during the patterning. In addition, the upper processing temperature for these materials, ranging from 350 to 400.degree. C., is too high for a protection film of a TFT. In general, when the processing temperature for the insulation or protection film is higher than 250.degree. C., the TFT characteristics may be affected by temperature. Also, the dielectric constant of polyimide is 3.4 to 3.8, similar to that of SiNx, 3.5. Therefore, a parasitic capacitance can not be sufficiently reduced.
It is evident that the problem associated with the stepped surface can be solved by the use of a material that has a smooth surface when applied for a protection or insulation layer. However, it is difficult to select such a material, taking into account various conditions/environment of an LCD. The following conditions should be met for a material used as an insulation or protection film.
First, the material should have a low dielectric constant when used for electrical insulation such as gate insulation, to prevent errors in the TFT operation by parasitic capacitance. The dielectric constants of SiNx and SiO.sub.2 for a conventional use are about 7 and 4, respectively. Second, the material should have a superior insulation property: high intrinsic resistivity. Third, when used as a protection film, the material should have a good adhesion property to ITO which is deposited on the protection film to form a pixel electrode.